A New Path Delay Fault Test Scheme Based on Delay Inertia
碩士 === 國立交通大學 === 電子工程系 === 91 === Correct operation of a logic circuit requires propagation delays of all paths in the circuit to be smaller than the intended clock interval. Defects and/or random variations in process parameters often cause propagation delays to fall outside the desired...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2003
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| Online Access: | http://ndltd.ncl.edu.tw/handle/32144946592157644448 |