Design and Automatic Generation for Universal Memory Built-In Self-Test System
碩士 === 國立成功大學 === 電機工程學系碩博士班 === 92 === In this Thesis, we propose a high speed universal memory BIST architecture for the heterogeneous embedded memory cores in SOCs. A novel encoding scheme is proposed for our architecture to reduce the complexity and improve the test efficiency of physical sign...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/40988081345700142299 |