Global Placement by Circuit Partitioning with Hyperedge Clique ModelingGlobal Placement by Circuit Partitioning with Hyperedge Clique Modeling
碩士 === 元智大學 === 資訊工程學系 === 93 === As VLSI technology advances, more transistors will be on a chip. In standard cell designs, transistors are grouped into cells of the same height to perform some basic logic function. There will be more than a million cells in a VLSI design. Placement of these cells...
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| Format: | Others |
| Language: | en_US |
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2005
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| Online Access: | http://ndltd.ncl.edu.tw/handle/39026823847514684108 |