Wire Width Sizing for Delay and Yield Optimization

碩士 === 元智大學 === 資訊工程學系 === 93 === In this paper, two issues about wire width are investigated. The first one is that “Is the minimum wire width under the minimum wire pitch for a process technology good enough from the perspective of timing performance?” The second is that “Is delay sensitive to wir...

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Bibliographic Details
Main Authors: Jia-Xun Yang, 楊佳勳
Other Authors: Rung-Bin Lin
Format: Others
Language:en_US
Published: 2005
Online Access:http://ndltd.ncl.edu.tw/handle/85931652717055393059