λ-Geometry Clock Tree Construction with Wirelength and Via Minimization
碩士 === 國立清華大學 === 資訊工程學系 === 94 === In deep sub-micron VLSI technologies, the interconnect delay has become a dominant factor affecting performance of ICs. Wirelength reduction is the most fundamental objective in the P&R stage. Compared with traditional Manhattan architecture, X-architecture an...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/37791968756278712335 |