Buffer Insertion for ASIC and FPGA Designs
碩士 === 國立清華大學 === 資訊工程學系 === 95 === With the technology process going into nanometer regime, the interconnect delay is a crucial determining factor of circuit performance in modern VSLI designs. Buffer insertion is one of the effective technique to improve the circuit performance. We explore two dif...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2007
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| Online Access: | http://ndltd.ncl.edu.tw/handle/51612808809154222102 |