Zero Skew Gated Clock Tree Design
碩士 === 中原大學 === 電子工程研究所 === 96 === In synchronous sequential circuits, clock tree is used for synchronizing all flip-flops in a chip. Thus, clock skew minimization is very important in the clock tree synthesis. The load-matching technique has been recognized as one of the most effective techniques t...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/13119401179743539419 |