| Summary: | 博士 === 國立成功大學 === 微電子工程研究所碩博士班 === 96 === In this dissertation, the hot-carrier-induced degradation in 0.35 μm n-type self-aligned lateral double-diffused MOSFET (LDMOS) and p-type drain-extended MOSFET (DEMOS) devices are studied.
When the nLDMOS device is used in a power switching circuits with an unclamped inductive load, the off-state avalanche breakdown occurs during on-state to off-state transient. The device degrades because of the high electric field and impact ionization located near the drain side poly-gate edge. The main mechanism of device degradation is the interface states and positive oxide-trapped charges created by breakdown-induced hole injection. The interface states degrade device turn-on resistance (Ron) however
positive oxide-trapped charges reduce the series resistance. The degradation has the tendency to saturate, which in consistent with the saturation of interface states and oxide-trapped charges generation. Moreover, increasing the device drift drain (NDD) region dosage can reduce the generation of interface states, leading to an improved degradation.
Besides Ron degradation, the off-state breakdown voltage (BVdss) increases while off-state avalanche breakdown occurs. It is suggested that the main mechanism of BVdss increase is the hole trapping created by hole injection. TCAD simulation reveals that hole trapping attract mirror electrons at Si/SiO2 surface and lower the potential contour crowding and reduce lateral and vertical electric field under drain side spacer. As a consequence, the impact ionization rate at breakdown point is lowered, leading to a higher breakdown voltage.
While the nLDMOS devices operate on on-state, the devices degrade due to high operating voltage and high electric field. The location of hot-carrier-induced interface states varies with different stress gate voltage. The interface states located in accumulation region under poly-gate have little effect on Idlin degradation. As a result, interface states located in drain-side spacer region dominate Idlin degradation when interface states located in channel region are negligible. In our experiment, increasing
NDD dosage results in improved Idlin degradation. TCAD simulations reveal that high NDD dosage increases impact ionization rate in accumulation and channel regions, but reduces impact ionization rate in spacer region, leading to an improved Idlin degradation.
Finally, the drain current shifts after hot carrier stress in pDEMOS transistors is studied. The drain saturation (Idsat) and linear current (Idlin) both increase after hot carrier stress due to hot electron injection and electron trapping. Electron trapping reduces the resistance of p-drift region hence increases drain current. Moreover, the current shifts are dependent on the length of drain extended region under poly gate. Device with longer drain extended under poly produces less current increment after Igmax stressing. TCAD simulation reveals that the path of current flow under Idlin and Idsat condition can explain the relation between the drain extended overlap and the current shifts.
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