A Low-Cost On-Chip SoC Debug Platform with Hardware Breakpoint Insertion and Single Step Capabilities for IP Cores
碩士 === 國立成功大學 === 電機工程學系碩博士班 === 96 === With the scaling down of feature sizes, integrating large and complex design into a single chip is becoming the main trend in IC design. However, such system-on-a-chip (SoC) design methodology introduces many problems as well. Besides circuit/system design, th...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/00643939913423821897 |