A Low-Cost On-Chip SoC Debug Platform with Hardware Breakpoint Insertion and Single Step Capabilities for IP Cores
碩士 === 國立成功大學 === 電機工程學系碩博士班 === 96 === With the scaling down of feature sizes, integrating large and complex design into a single chip is becoming the main trend in IC design. However, such system-on-a-chip (SoC) design methodology introduces many problems as well. Besides circuit/system design, th...
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| Format: | Others |
| Language: | en_US |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/00643939913423821897 |
| Summary: | 碩士 === 國立成功大學 === 電機工程學系碩博士班 === 96 === With the scaling down of feature sizes, integrating large and complex design into a single chip is becoming the main trend in IC design. However, such system-on-a-chip (SoC) design methodology introduces many problems as well. Besides circuit/system design, the most critical problem is testing and debugging of SoC systems. In this thesis, we present a SoC debug platform to address this problem.
The developed debug platform supports multi-core debug technology inclusive of cycle-based breakpoint insertion and single step for general purpose cores/IP on a SoC chip. We allow users to suspend and restore the normal operation to obtain detailed information in the CUDs (Cores Under Debug). This platform has the advantages of low area overhead by reusing test components and high flexibility by providing several debug modes. Also, we develop a graphic user interface to support this on-chip debug platform. With this design automation tool, users can easily control the debug operation and receive traced results to identify the root-cause of failures in the silicon easily and efficiently. Experimental results show that the proposed debug platform is a practical solution for silicon debug problem.
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