A 10-Gb/s CMOS Clock and Data Recovery Circuit with Data-Deskew Buffers in the Closed Loop
碩士 === 國立交通大學 === 電機學院碩士在職專班電子與光電組 === 96 === This thesis proposes a data-deskew clock and data recovery (CDR) architecture for the on-chip multi-channel timing recovery. This CDR recovers the 10-Gb/s/ch burst data packet by adjusting the data delay in the digitally controlled delay line (DCDL). Aft...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2007
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/59977775057034141555 |