| Summary: | 碩士 === 國立交通大學 === 電機學院碩士在職專班電子與光電組 === 96 === This thesis proposes a data-deskew clock and data recovery (CDR) architecture for the on-chip multi-channel timing recovery.
This CDR recovers the 10-Gb/s/ch burst data packet by adjusting the data delay in the digitally controlled delay line (DCDL). After the acquisition of the optimal sampling phase, the midpoint of data period aligns to the sampling clock. The data skew between channels is also compensated.
This CDR is first-order and therefore inherently stable. It can track the specified 1000-ppm frequency error as long as the peak-to-peak clock jitter between the transmitter and the receiver sites is confined to the specification. And, the closed loop characterizes the high-band-limited jitter in this system.
All building blocks adopt digital circuits. Fast acquisition (110-bit time in typical case) is achieved by the majority-vote scheme in the confidence counter. Two critical designs exist in this digital-circuit CDR: 1) high-speed large-swing CMOS DCDL deign, and 2) meeting the loop-latency constraint.
In addition, a digital implementation of the 10-Gb/s transceiver is realized in TSMC 0.13-μm CMOS technology.
|
|---|
