5-Gb/s Low Power On-Chip Pulse Signaling Interface
碩士 === 國立交通大學 === 電機與控制工程系所 === 96 === In this thesis, we propose an on-chip pulse signaling communication. It can be used for long distance and low power interconnection on SOC. The pulse signaling communication consists of a transmitter, an on-chip transmission-line and a receiver. By increase the...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2007
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| Online Access: | http://ndltd.ncl.edu.tw/handle/80821266856478191119 |