Transaction Level Modeling of the High Performance Bus Design with OCP Interface
碩士 === 國立成功大學 === 電機工程學系碩博士班 === 97 === Due to the rapid progress in IC design and development, the number of integrated IP cores in SOC designs is increasing, and the communication between IP cores are increasing accordingly. However, the traditional bus design is out-of-date to deal with the large...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/31169620363597740423 |