A Low-Cost On-Chip SOC Debug Platform with Multiple Clock Domain Breakpoint Insertion Capabilities
碩士 === 國立成功大學 === 電機工程學系碩博士班 === 97 === As more and more IP cores are integrated into a SoC, designs equipped with multiple clocks have become popular. In such designs data are frequently transferred from one clock domain to another. This cross-clock-domain data transfer feature, however, also compl...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/86953798692384831452 |