A SoC Debug Platform with Inside-Core Adjustment and Event Trigger Capabilities
碩士 === 國立成功大學 === 電機工程學系碩博士班 === 97 === With the rapid development of semiconductor manufacturing technology, integrating various IP cores into a System-on-Chip (SoC) has become a quite popular manner in IC design. However, the low observability and controllability of such complex silicon chips als...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/72124643768689483740 |