| Summary: | 碩士 === 國立成功大學 === 電機工程學系碩博士班 === 97 === Since the development of the semiconductor technology has been greatly advanced, SoC designs integrate an increasing number of cores with different functionality to reduce the total cost of products. However, the SoC-based design methodology also induces many challenges. In order to test an SoC effectively, expensive ATE with large memory, high frequency, and great accuracy is usually used. Besides, as more and more transistors with smaller size are squeezed into SoC, timing-related defects have become one of the major causes that make an SoC unfunctional. Testing the timing defects of SoC with low cost has become one of the crucial issues that need to be addressed. This thesis presents an on-chip clock generation architecture for at-speed delay test of IEEE 1500 wrapped cores. In this work, we embedded a clock generator (CG) in the IEEE 1500 test
wrapper to generate the clock pulses not only for logic belonging to single clock domain but also for crossing clock domains. Output boundary scan cells are also controlled by CG to capture fault effects from register to primary outputs. We also integrate the 1500-wrapped cores with CGs into the SoC test platform. A delay test flow is also developed. Experimental results confirm the effectiveness of the proposed on-chip clock generation architecture.
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