Warpage Simulation of Fan-Out Wafer Level Chip Scale Package
碩士 === 國立成功大學 === 機械工程學系碩博士班 === 97 === Wafer level packaging is an important development trend for IC package design. The fan-out wafer level package discussed here has the flip chip form which uses thin-film redistribute then uses solder bump to connect the package to the printed wiring board dir...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/37274369936517085920 |