A Bus Circuit Design with Dynamic Voltage/Frequency Scaling and Repeater Insertion
碩士 === 國立交通大學 === 電機與控制工程系所 === 97 === This thesis proposes a bus circuit using repeater insertion to reduce its power consumption and area. Moreover, we use a timing measurement circuit to estimate eye opening and jitter. According to the eye opening, we can determine if the supply voltage or the f...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/99647596644232328251 |