Low-Error and Area-Efficient Fixed-Width Multiplier with Fixed Compensation Circuit
碩士 === 長庚大學 === 電機工程學系 === 98 === In this thesis, we propose a new error compensation circuit to lower IC vector compensation error. By removing the less-compensation situations in the dual-tree design [18], the compensation error can be lowered. To construct the error compensation circuit only by t...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Published: |
2010
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/64135996791406007853 |