Design and Implementation of Noise-Tolerant Dynamic CMOS Circuit
碩士 === 長庚大學 === 電機工程學系 === 98 === In this thesis, we proposed a contention-relaxed isolated noise-tolerant (CR-INT) technique and a true-single-phase-clocking based noise-tolerant (TSPC-NT) technique to enhance the noise immunity of dynamic CMOS circuits by raising the source voltage of pull-down ne...
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| Format: | Others |
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2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/99910578366464715775 |