| Summary: | 碩士 === 長庚大學 === 電機工程學系 === 98 === In this thesis, we proposed a contention-relaxed isolated noise-tolerant (CR-INT) technique and a true-single-phase-clocking based noise-tolerant (TSPC-NT) technique to enhance the noise immunity of dynamic CMOS circuits by raising the source voltage of pull-down network and preventing the noise signal interfering with the floating node, respectively. The proposed CR-INT technique is modified from INT technique [31], which is a mechanism dedicated to isolate noise tolerant circuits from noise interference. In CR-INT design, we modified the mechanism to trigger noise-tolerant transistor and removed the leakage path in [31] to avoid signal contention occurring. Moreover, we adopted the inverse of CLK signal to isolate the noise-tolerant transistor from noise interference, which can achieve higher noise immunity with less performance sacrifice in terms of power consumption and computation delay. The proposed TSPC-NT technique is to isolate and filter out noise signal in the inputs of dynamic circuits. In this way, the signal contention issues associated with noise-tolerant techniques can be avoided. Therefore, we can achieve higher noise immunity with less performance sacrifice in terms of power consumption, computation delay, and chip area. Experimental result shows that the proposed 16-bit CR-INT Carry Look-ahead adder (CLA) can achieve 1.2X average noise threshold energy (ANTE) improvement with 43% power consumption saving and 14% computation delay acceleration as compared with the 16-bit INT CLA under TSMC 0.18μm process. The proposed 16-bit TSPC-NT CLA can achieve 3X ANTE improvement with 6% power consumption saving and the same computation delay as compared with the 16-bit XOR-NT [40] CLA under TSMC 90nm process.
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