Clock Design Methodology for High Reliability
博士 === 中原大學 === 電子工程研究所 === 98 === In a synchronous sequential circuit, the clock signal is used to define a relative time reference for the movement of data. The clock skew is the maximum difference among the clock latencies (i.e., clock delays) from the clock source to flip-flops. Since the clock...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/15962988364951040865 |