Clock Design Methodology for High Reliability

• Main Authors: Chia-Ming Chang, 張家銘
• Other Authors: Shih-Hsu Huang
• Format: Others
• Language: en_US
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/15962988364951040865

博士 === 中原大學 === 電子工程研究所 === 98 === In a synchronous sequential circuit, the clock signal is used to define a relative time reference for the movement of data. The clock skew is the maximum difference among the clock latencies (i.e., clock delays) from the clock source to flip-flops. Since the clock skew is crucial to performance, a lot of research efforts have been made to the management of clock skew. In the era of deep sub-micron, the manufacturing technology keeps growing. In addition to area minimization, performance optimization, and low power consumption, reliability is also a serious issue. In this dissertation, we study high-reliability clock design methodology. Two clock design approaches are presented below. First, we study the clock design for peak current reduction. Multi-domain clock skew scheduling can be used to arrange the arrival time of every register to avoid registers switching at the same time. However, solving this multi-domain clock skew scheduling is a very time-consuming problem. In this dissertation, we propose several efficient techniques to improve the run time. Our works includes (1) ASAP and ALAP skew scheduling (to reduce the variables without pruning the optimal solutions), and (2) Zone-based skew scheduling (to separate the variables into several smaller zones). Our experimental results show that our approaches can reduce the run time significantly. Second, we propose a design methodology to minimize the skew caused by NBTI effect in a gated clock tree. The main idea of clock gating is to shutdown the portions of circuit which are not in ‘active’ mode so that the power consumption can be reduced. Different active probabilities of clock gates cause different delay degradations. Setting the active probabilities of enable signals at the same level to the same value is an easy way to eliminate the aging skew. However, it requires a lot of power consumption. In this dissertation, we develop a critical-PMOS-aware design methodology to reduce the number of critical PMOSs, which are the necessary part to deal with and to compensate the active probability. Experimental results show that our approach is a very useful technology to solve this problem.