A Post-Processing Approach to Minimize TSV Number in High-Level Synthesis
碩士 === 中原大學 === 電子工程研究所 === 98 === Three Dimensional (3D) IC technology stacks multiple integrated chips and its application is more and more popular. Therefore, developing EDA tools for the requirement of 3D architecture becomes urgent and important. In this thesis, we present an integer linear...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/44769486642214863678 |