Low-Power Algorithmic Noise-Tolerant Circuit Design Based on Gated Main Arithmetic Block and Precise Fixed-Width Reduced Precision Redundancy
碩士 === 長庚大學 === 電機工程學系 === 99 === In this thesis, we proposed a new low-power algorithmic noise-tolerant architecture design and applied it in a multiplier circuit, which can lower its power consumption while maintain its system reliability at the same time. Algorithmic noise-tolerant circuit design...
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| Format: | Others |
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2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/68074622123599444855 |