High Level Synthesis Methodology for Highly Testable and Nonzero Clock Skew Low Power Design
博士 === 中興大學 === 資訊科學與工程學系所 === 99 === Modern consumer electronic applications, including smart phone and automotive electronics, become very complicated. The time-to-market requirement of such applications has become a serious challenge for contemporary register transfer level (RTL) design flow. Ele...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/18059951135258306266 |