Peak Current Minimization for Activity Driven Gated Clock Tree
碩士 === 中原大學 === 電子工程研究所 === 100 === In a modern integrated circuit, the power consumption of clock tree often occupies a significant fraction of the power consumed of the whole chip. Clock gating has been recognized as a useful technique to reduce the power consumption of clock tree. Activity drive...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2012
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| Online Access: | http://ndltd.ncl.edu.tw/handle/12099761369197561931 |