Peak Current Minimization for Activity Driven Gated Clock Tree

• Main Authors: Shih-Ji Wang, 王詩集
• Other Authors: Shih-Hsu Huang
• Format: Others
• Language: zh-TW
• Published: 2012
• Online Access: http://ndltd.ncl.edu.tw/handle/12099761369197561931

碩士 === 中原大學 === 電子工程研究所 === 100 === In a modern integrated circuit, the power consumption of clock tree often occupies a significant fraction of the power consumed of the whole chip. Clock gating has been recognized as a useful technique to reduce the power consumption of clock tree. Activity driven clock tree is a design methodology for the planning of clock gating in the high level synthesis stage. However, if we only use AND gates for the construction of activity-driven clock tree, the simultaneous switching of these AND gates may cause a huge peak current (since these AND gates have the same charging and discharging activities). In this thesis, we present an approach to replace some AND gates by NAND gates. By carefully considering the charging and discharging activates of each control step, our approach can effectively minimize the peak current of an activity driven gated clock tree. Benchmark data consistently show our approach can reduce 40.18% peak current in average.