Testing of TSV-induced Small Delay Faults for Three Dimensional Integrated Circuits
碩士 === 國立臺灣大學 === 電子工程學研究所 === 100 === Through silicon via (TSV) is a widely used interconnect technology in three dimensional integrated circuits (3D ICs). This paper shows that defective TSVs can induce small delay faults in surrounding logic gates. We present simulation results of TSV-induced s...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2012
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| Online Access: | http://ndltd.ncl.edu.tw/handle/82927954241531590070 |