| Summary: | 碩士 === 中原大學 === 電子工程研究所 === 102 === Due to technology scaling, the leakage power reduction problem has attracted a lot of attention. Besides, in a circuit, glitches (spurious transitions) happen if a signal goes through several state changes before it reaches its steady state within a clock cycle.
Although clock skew can be used to improve circuit speed and power consumption, very few researches efforts have been paid to the utilization of clock skew in the leakage power reduction problem.
In this thesis, we point out that, in addition to data path synthesis (gate sizing and buffer insertion), clock skew can also be utilized for further power reduction. Based on this observation, we propose an integer linear programming for the simultaneous application of data path synthesis (gate sizing and buffer insertion) and clock skew scheduling. Note that our approach is the first work to deal with this problem. Compared with previous works, experimental results consistently show that our approach can achieve better results.
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