3D IC Test Scheduling under Power and Test Pads Constraints
碩士 === 中原大學 === 電子工程研究所 === 104 === As the system-on-chip (SoC) design complexity continue to increase, three-dimensional integrated circuit (3D IC) design has become an industry trend. However, the testing of a 3D IC is more difficult than the testing of a 2D IC. As the same as a 2D IC, the core of...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2016
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| Online Access: | http://ndltd.ncl.edu.tw/handle/6293he |