| Summary: | 碩士 === 中原大學 === 電子工程研究所 === 104 === As the system-on-chip (SoC) design complexity continue to increase, three-dimensional integrated circuit (3D IC) design has become an industry trend. However, the testing of a 3D IC is more difficult than the testing of a 2D IC. As the same as a 2D IC, the core of a 3D IC must use the TAM Bus to connect with the automatic test equipment (ATE). But in for a 3D IC, its testing includes two parts: pre-bond testing and post-bond testing. The decision on the assignment of test access mechanism (TAM) Bus and the number of test pads of each layer becomes more complicated. Thus, our objective is to minimize the total test time of the 3D IC under the constraints on power consumption and the constraints on the number of test pad.
In this thesis, we propose an integer linear programming (ILP) approach to perform the 3D IC test scheduling under test pads and peak power constraints. Different from previous works, our approach can minimize both test application time and the number of required test pads. Experimental results show that our approach achieves better results than previous works.
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