A Low Power Pipeline ADC Using Time-Domain Transfer Technique
碩士 === 國立臺灣大學 === 電子工程學研究所 === 104 === This thesis proposes a 10bit, 300MHz pipeline ADC. Due to the design difficulty in advanced process and large power consumption of operation amplifier(opamp). The proposed work wants to avoid using operation amplifier. At the same time, the time resolution in a...
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ndltd-TW-104NTU054280722017-04-29T04:31:56Z http://ndltd.ncl.edu.tw/handle/20038403707009700376 A Low Power Pipeline ADC Using Time-Domain Transfer Technique 一個利用時間軸轉換技巧的低功率導管式類比數位轉換器 Yu-Wei Chuang 莊郁暐 碩士 國立臺灣大學 電子工程學研究所 104 This thesis proposes a 10bit, 300MHz pipeline ADC. Due to the design difficulty in advanced process and large power consumption of operation amplifier(opamp). The proposed work wants to avoid using operation amplifier. At the same time, the time resolution in advanced process becomes more accuracy. So the time domain signal rather than voltage domain signal is used in the proposed work to do the signal process. Normally, the input signal and reference voltage is subtracted in voltage domain. In this thesis, the subtraction is realized in time domain to avoid the overshoot problem due to the delay of comparator. The active area of the proposed work is about 0.694mm2. The ENOB can reach 9.49bit in post-simulation, whose power consumption is 5.2mW and FoM is 22fJ/conversion-step. Unfortunately, the noise of the proposed work was not carefully considered. So, the performance of chip is limited under 5bit. With these problem, the noise analysis and evolve way will be discussed in the thesis. 陳信樹 2016 學位論文 ; thesis 112 en_US |
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碩士 === 國立臺灣大學 === 電子工程學研究所 === 104 === This thesis proposes a 10bit, 300MHz pipeline ADC. Due to the design difficulty in advanced process and large power consumption of operation amplifier(opamp). The proposed work wants to avoid using operation amplifier. At the same time, the time resolution in advanced process becomes more accuracy. So the time domain signal rather than voltage domain signal is used in the proposed work to do the signal process. Normally, the input signal and reference voltage is subtracted in voltage domain. In this thesis, the subtraction is realized in time domain to avoid the overshoot problem due to the delay of comparator.
The active area of the proposed work is about 0.694mm2. The ENOB can reach 9.49bit in post-simulation, whose power consumption is 5.2mW and FoM is 22fJ/conversion-step. Unfortunately, the noise of the proposed work was not carefully considered. So, the performance of chip is limited under 5bit. With these problem, the noise analysis and evolve way will be discussed in the thesis.
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陳信樹 |
author_facet |
陳信樹 Yu-Wei Chuang 莊郁暐 |
author |
Yu-Wei Chuang 莊郁暐 |
spellingShingle |
Yu-Wei Chuang 莊郁暐 A Low Power Pipeline ADC Using Time-Domain Transfer Technique |
author_sort |
Yu-Wei Chuang |
title |
A Low Power Pipeline ADC Using Time-Domain Transfer Technique |
title_short |
A Low Power Pipeline ADC Using Time-Domain Transfer Technique |
title_full |
A Low Power Pipeline ADC Using Time-Domain Transfer Technique |
title_fullStr |
A Low Power Pipeline ADC Using Time-Domain Transfer Technique |
title_full_unstemmed |
A Low Power Pipeline ADC Using Time-Domain Transfer Technique |
title_sort |
low power pipeline adc using time-domain transfer technique |
publishDate |
2016 |
url |
http://ndltd.ncl.edu.tw/handle/20038403707009700376 |
work_keys_str_mv |
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