TSV-Aware Wrapper Chain Optimization for Three-Dimensional SoCs
碩士 === 中原大學 === 電子工程研究所 === 106 === A system-on-Chip (SoC) design consists of many embedded cores. In order to test these embedded cores, modular wrapper design needs to connect scan elements to form test wrapper chains. Since the longest test wrapper chain affects the test time, how to balance thes...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2018
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| Online Access: | http://ndltd.ncl.edu.tw/handle/556e2f |