Concurrent Timing-Driven Layer Assignment for Multiple Nets at Advanced Technology Nodes
碩士 === 國立交通大學 === 電子研究所 === 106 === Timing optimization is essential for IC design; only correct timing can ensure correct data synchronization. At advanced technology nodes, RC effect makes the metal resistance on lower layers more than twenty times bigger than those on higher layers. Using the met...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2017
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| Online Access: | http://ndltd.ncl.edu.tw/handle/4hna7g |