Memory Partitioning and Optimization of On-Chip Accelerators with High-Level Synthesis
碩士 === 國立清華大學 === 資訊工程學系所 === 106 === Current researches in the design space exploration for accelerators mainly rely on either RTL-based flow or High-Level Synthesis flow. However, both of them are very time-consuming. Pre-RTL tools, such as Aladdin, can directly analyze designs in high-level langu...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2017
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| Online Access: | http://ndltd.ncl.edu.tw/handle/24zvgm |