A Novel Test Generation Method for Small-Delay Defects with User-defined Fault Model
碩士 === 國立成功大學 === 電機工程學系 === 107 === To ensure the quality of high-performance VLSI chips, small delay defects (SDDs) are widely considered in the industry. Several ATPG tools have been developed to deal with these defects, with timing information employed to help select long paths that are more sen...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2019
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| Online Access: | http://ndltd.ncl.edu.tw/handle/d94h5w |