| Summary: | 碩士 === 國立成功大學 === 電機工程學系 === 107 === To ensure the quality of high-performance VLSI chips, small delay defects (SDDs) are widely considered in the industry. Several ATPG tools have been developed to deal with these defects, with timing information employed to help select long paths that are more sensitive to small delays and hence high-quality tests can be generated. However, these methods usually require long test generation time and may result in large pattern count.
In this thesis, we propose a novel test generation method for SDDs based on a common path stem concept. By extracting the common path stems of those long paths in a circuit, one can use the user-defined fault model (UDFM) to set some conditions on the path stems and thus force the fault effects of SDDs to propagate through long paths, such that a compact pattern set can be generated and high delay test coverage (DTC) can be achieved for SDDs. Compared with the well-known timing-aware ATPG, our proposed method can reduce 19.2% pattern count and increase 0.74% DTC on average for ISCAS89 and IWLS05 benchmark circuits.
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