$Compressively-strained, buried-channel $Si_{0.7}$Ge$_{0.3}$ p-MOSFETs fabricated on SiGe virtual substrates using a 0.25 µm CMOS process$

Compressively-strained, buried-channel $Si_{0.7}$Ge$_{0.3}$ p-MOSFETs fabricated on SiGe virtual substrates using a 0.25 µm CMOS process

Enhanced performance is demonstrated from a buried, compressively strained-Si0.7Ge0.3 p-MOSFET fabricated on a relaxed Si0.85Ge0.15 using a high thermal budget 0.25 µm CMOS process. The devices are designed to be fully compatible with a strained-Si CMOS process but offers a number of potential benef...

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Bibliographic Details
Main Authors:	Temple, Matthew P. (Author), Paul, Douglas J. (Author), Tang, Yue T. (Author), Waite, Andrew M. (Author), Cerrina, Claudia (Author), Evans, Alan G.R (Author), Li, Xiabbing (Author), Zhang, Jing (Author), Olsen, Sarah H. (Author), O'Neill, Anthony G. (Author)
Format:	Article
Language:	English
Published:	2004-03.
Subjects:	Article
Online Access:	Get fulltext

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Compressively-strained, buried-channel $Si_{0.7}$Ge$_{0.3}$ p-MOSFETs fabricated on SiGe virtual substrates using a 0.25 µm CMOS process

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